As integrated circuits continue to increase in complexity and total number of devices, the probability of a failure may remain the same or decrease, but the probability of an integrated circuit containing a fault increases. In many integrated circuits, a certain degree of redundancy is built into the integrated circuit that will permit the faulty portions to be replaced. However, the faulty portions of the integrated circuit must first be detected.
A technique that can be used to detect transistor failures in an integrated circuit is to measure the quiescent current (IDDQ). If the IDDQ measurement is different from an expected range of values, then it is determined that there is a failure of at least one transistor in the integrated circuit. By partitioning the integrated circuit into different regions, typically along different power-domains, it may be possible to narrow down the location of the failed transistor and implement a remedy.
In a prior art technique, the testing of an integrated circuit makes use of a switched array structure and can involve powering up individual power-domains and then scanning in test vectors for the powered power-domain and scanning out the results. The entire integrated circuit can then be tested by repeating the powering up, scanning in, and scanning out for each of the power-domains.
One disadvantage of the prior art is the powering up, scanning in, and scanning out of each of the individual power domains can be time consuming. With a complex integrated circuit, such as a system on a chip (SOC), the total testing time can be great. This can reduce the number of integrated circuits that can be tested, perhaps resulting in the need for a large number of testing stations (which can be expensive) to meet production and testing demands.
A second disadvantage of the prior art is that logic isolation between the power domains is required. Logic isolation adds more gates and can increase logic complexity as well as having a potentially adverse effect upon critical timing paths across power domains. Additionally, design for test (DFT) requirements have to be added to each power domain. DFT requirements for each power domain can require that clock signals for each power domain may have to be bypassed during test mode and that power control signals to the power domains remain on during testing. This can lead to the need of a separate scan chain for each power domain.
A third disadvantage of the prior art is that by testing individual power-domains, the individual power-domains need to be isolated from one another. To isolate the power-domains, isolation buffers need to be implemented in the integrated circuit. The isolation buffers tend to be large, in a typical SOC, to properly isolate the power-domains, the chip area consumed by the isolation buffers may account for approximately 10 percent of the total chip area.
Yet another disadvantage of the prior art is that it prohibits the measurement of sub-power-domain IDDQ since internal VDD nodes are shorted together. By not permitting sub-power-domain measurement of IDDQ, fine grained failed transistor testing is not possible, thereby reducing the ability to accurately locate a faulty transistor.